1. Field of the Invention
This invention relates generally to nonvolatile memory array structure and operation. More particularly, this invention relates to NOR nonvolatile memory device structures, peripheral circuits for NOR nonvolatile memory devices and methods for operation of NOR nonvolatile memory devices.
2. Description of Related Art
Nonvolatile memory is well known in the art. The different types of nonvolatile memory include Read-Only-Memory (ROM), Electrically Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), NOR Flash Memory, and NAND Flash Memory. In current applications such as personal digital assistants, cellular telephones, notebook and laptop computers, voice recorders, global positioning systems, etc., the Flash Memory has become one of the more popular types of Nonvolatile Memory. Flash Memory has the combined advantages of the high density, small silicon area, low cost, and can be repeatedly programmed and erased with a single low-voltage power supply voltage source.
The Flash Memory structures known in the art employ a charge retaining mechanism such as a charge storage phenomena and a charge trapping phenomena. In the charge storage mechanism, as with a floating gate nonvolatile memory, the charge representing digital data is stored on a floating gate of the device. The stored charge modifies the threshold voltage of the floating gate memory cell to determine the digital data stored. In a charge trapping mechanism, as in a Silicon-Oxide-Nitride Oxide-Silicon (SONOS) or Metal-Oxide-Nitride-Oxide-Silicon (MONOS) type cell, the charge is trapped in a charge trapping layer between two insulating layers. The charge trapping layer in the SONOS/MONOS devices has a relatively high dielectric constant (k) such as Silicon Nitride (SiNx).
A present day flash nonvolatile memory is divided into two major product categories such as the fast random-access asynchronous NOR flash nonvolatile memory and the slower serial-access synchronous NAND flash nonvolatile memory. NOR flash nonvolatile memory devices, as presently designed are the high pin-count memory with multiple external address and data pins along with appropriate control signal pins. One disadvantage of NOR flash nonvolatile memory is, as the density is doubled, the number of the required external pin count increases by one due to the adding of one more external address pin. In contrast, NAND flash nonvolatile memory has an advantage of having a smaller pin-count than NOR with no address input pins. As density increases, the NAND flash nonvolatile memory pin count is always kept constant. Both main-streamed NAND and NOR flash nonvolatile memory cell structures in production today use a one charge retaining (charge storage or charge trapping) transistor memory cell that stores one bit of data as charge or as it commonly referred to as a single-level program cell (SLC). They are respectively referred as one-bit/one transistor NAND cell or NOR cell, storing a single-level programmed data in the cell.
The NAND and NOR flash nonvolatile memory provide the advantage of in-system program and erase capabilities and have a specification for providing at least 100K endurance cycles. In addition, both single-chip NAND and NOR flash nonvolatile memory product can provide giga-byte density because their highly-scalable cell sizes. For instance, presently a one-bit/one transistor NAND cell size is kept at ˜4λ2 (A being a minimum feature size in a semiconductor process), while NOR cell size is ˜10λ2. Furthermore, in addition to storing data as a single-level program cell having two voltage thresholds (Vt0 and Vt1), both one transistor NAND and NOR flash nonvolatile memory cells are able to store at least two bits per cell or two bits/one transistor with four multi-level threshold voltages (Vt0, Vt1, Vt2 and Vt03) in one physical cell.
NOR flash memories cells are arranged in an array, of rows and columns in a NOR-like structure. All the NOR Flash cells on each row share the same word line. The drain electrodes that are common to two cells on each column are commonly connected to the bit line (BL) associated with each column. Sources of each of the NOR flash cells of each of the rows of the array are commonly connected to the source lines SL that are commonly connected and are often connected to the ground reference voltage source.
Currently, the highest-capacity of a single-chip double polycrystalline silicon gate NAND flash nonvolatile memory chip is 64 Gb. In contrast, a double polycrystalline silicon gate NOR flash nonvolatile memory chip has a density of 2 Gb. The big gap between NAND and NOR flash nonvolatile memory density is a result of the superior scalability of NAND flash nonvolatile memory cell over a NOR flash nonvolatile memory. A NOR flash nonvolatile memory cell requires 5.0V drain-to source (Vds) to maintain a high-current Channel-Hot-Electron (CHE) programming process. Alternately, a NAND flash nonvolatile memory cell requires a voltage difference between the drain to source of zero volts (0.0V) for a low-current Fowler Nordheim channel tunneling program process. This results in the one-bit/one transistor NAND flash nonvolatile memory cell size being approximately one-half that of a one bit/one transistor NOR flash nonvolatile memory cell. This permits a NAND flash nonvolatile memory device to be used in applications that require huge data storage. A NOR flash nonvolatile memory device is extensively used as a program-code storage memory which requires less data storage and requires fast and asynchronous random access.